Yamaha J-3000 Service Manual Page 80

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IC13
IC14
IC17
IC15
CB4
CB6
IC21
CB7
CB8
IC16
IC18
CB3
A
1
2
3
4
5
6
7
8
9
10
BCDEFGH I JK
L MN
YSP-3000/YSP-30D/HTY-7030
80
All voltages are measured with a 10M/V DC electronic voltmeter.
Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
Schematic diagram is subject to change without notice.
DSP 2/2
WOOFER
WOOFER L
SUB
WOOFER
SW
FRONT
SURROUND
CENTER
3.3
0
3.3
0
3.3
4.9
0
2.5
2.5
1.7
0
1.7
1.7
0
3.3
0
5.0
3.3
0
3.3
1.7
3.3
2.5
0
5.0
0
3.3
4.9
0
2.5
2.5
0
3.3
2.9
3.3
2.9
2.9
2.9
2.9
2.9
2.9
2.9
3.3
3.3
0
0
0
0.1
0.1
3.2
3.2
3.3
3.1
0.1
3.3
3.3
2.9
3.3
2.9
0
3.3
2.9
3.3
2.9
0
2.9
0
2.9
2.9
0
3.1
0
0
0
1.7
1.6
3.2
3.2
0
1.7
3.3
3.3
0
0
00
03.3
00
02.9
02.9
02.9
02.9
02.9
0
3.3
3.3
0
3.3
2.9
2.9
2.9
3.3
2.9
2.9
3.3
2.9
2.9
02.9
1.7 2.9
1.6 2.9
3.2 2.9
3.2
3.2 0
3.2 3.3
0.1
3.3
3.3
0
0
0
0
0
1.3
0
3.3
3.3
0
1.3
1.3
0
1.3
0
3.3
0
1.3
0
0
1.3
0
1.3
3.3
1.7
1.7
1.7
0
1.3
3.3
0
1.3
3.3
0
0
1.3
1.3
0
3.3
3.3
0
1.7
1.7
3.3
3.3
0
1.3
0.1
0
0
0
0
0
1.3
2.9
2.9
2.9
2.9
2.9
2.9
2.9
2.9
2.9
2.9
2.9
1.3
0
3.3
1.3
0
3.3
2.9
2.9
2.9
3.1
0
3.1
3.3
0
1.3
2.9
2.9
1.3
0
3.2
0
1.3
0
3.3
1.3
1.3
0
0.2
0.2
0.2
1.3
0
3.3
0.2
3.3
3.3
3.3
0
1.3
1.3
0
1.3
0
0
3.3
1.3
0
0
3.3
0
3.3
3.3
0
1.6
3.3
1.3
0
3.3
3.3
3.3
1.3
0.1
0.1
3.2
3.3
0
1.3
3.2
3.2
3.2
1.7
3.3
0
1.6
3.3
0
1.3
1.7
0.1
0
3.3
0
0
0
3.3
3.3
0
1.3
0
0
3.3
0
0
0
0
1.3
0
0
0
1.3
3.3
3.3
0
0
3.3
3.3
3.3
0
3.3
0
3.3
3.3
1.3
No replacement part available.
サービス部品供給なし
DSP2
Sound equalization volume
DRAM FLASH ROM
DAC
(WOOFER)
DAC
(SUBWOOFER)
MX29LV160 CBTC-70G
Pin Multiplexing
EMIF32
L1P Cache
Direct Mapped
4K Bytes Total
Digital Signal Processors
L1D Cache
2-Way Set
Associative
4K Bytes Total
Clock Generator,
Oscillator and PLL
x4 through x25 Multipliers
/1 through /32 Dividers
Power-Down
Logic
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path BData Path A
B Register File
Control
Registers
C67x
TM
CPU
Control
Logic
In-Circuit
Emulation
Interrupt
Control
Te st
A Register File
.L1t
McASP1
McASP0
McBSP1
McBSP0
I2C1
I2C0
Timer 1
Timer 0
.S1t .M1t .D1 .D2 .M2t .S2t .L2t
GP1
GP0
HPI16
Enhanced
DMA
Controller
(16 channel)
L2 Cache/
Memory
4 Banks
64K Bytes
To ta l
(4-Way)
L2
Memory
DA610:
192K Bytes
DA601:
64K Bytes
R2 ROM
512K
Bytes
To ta l
IC13: D60YA003BPYP225
Decoder
1
3
2
5
4
GND
V
CC
IC14: TC7SH08FU
2-input AND gate
IN A
IN B
OUT Y
IC16: W9864G6GH-7
64 M x 4 banks SDRAM
DQ0
DQ15
UDQM
LDQM
CLK
CKE
A10
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
CELL ARRAY
BANK #2
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #0
CELL ARRAY
BANK #3
DATA CONTROL
CIRCUIT
DQ
BUFFER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #1
ROW DECODER
A0
A9
BS0
BS1
CS
RAS
CAS
WE
A11
ROW DECODER
COLUMN DECODER
SENSE AMPLIFIER
COLUMN DECODER
SENSE AMPLIFIER
ROW DECODER
ROW DECODER
BCKIN
LRCIN
DIN
MCLK DVDDAVDD
MUTEBSDIDEMSCKDSDLATI2SMODE CSBIWL ZERO
VOUTL
VOUTR
VMID
AGND DGNDVREFP VREFN
16 15
14
20 19 18 17 5
67
1
2
3
413
12
11
8
910
IC15, 17: WM8728
24-bit, 192 kHz stereo DAC
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX29LV160C T/B
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
X
-
D
E
C
O
D
E
R
ADDRESS
LATCH
AND
BUFFER
Y-PASS GATE
Y-DECODER
ARRAY
SOURCE
HV
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q15/A-1
A0-A19
CE#
OE#
WE#
RESET#
IC18: MX29LV160CBTC-70G
16M-bit CMOS single voltage 3V only flash memory
to INPUT_CB10
DIGITAL IN
Page 81
J4
to INPUT_CB11
Page 81 J6
to POWER (1)_CB507
Page 85 L6
to AMP_CB501
Page 83
A2
to DSP_CB1
Page 79
C8
Page view 79
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