Yamaha HTR-5940BL Service Manual Page 41

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41
RX-V459/HTR-5940/DSP-AX459
HTR-5935
RX-V459/HTR-5940/DSP-AX459
HTR-5935
IC DATA
IC2 : M30625MHP-A98GP (DSP P.C.B.)
Microprocessor
8
(3) (3) (3) (3)
8882
Port P0
Port P11 Port P14 Port P12
<VCC2 ports> (4)<VCC1 ports> (4)
NOTES:
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. Ports P11 to P14 exist only in 128-pin version.
4. Use M16C/62PT on VCC1=VCC2.
Watchdog timer
(15 bits)
Watchdog timer
(
Polynomial: X
16
+X
12
+X
5
+1
)
Clock synchronous serial I/O
(8 bit x 2 channels)
Watchdog timer
(15 bits)
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
Three-phase motor
control circuit
Timer (16 bit)
Output (timer A): 5
Input (timer B): 6
Internal peripheral functions
M16C/60 series 16-bit CPU core Memory
Multiplier
ROM
(1)
RAM
(2)
R0H R0L
R1H
R2
R3
A0
SB
USP
ISP
INTB
PC
FLG
A1
FB
R1L
DMAC
(2 channels)
D/A converter
(8 bit x 2 channels)
D/A converter
(
10 bit x 8 channels
Expandable up to 26 channels
)
UART or
clock synchronous serial I/O
(8 bit x 8 channels)
Port P13
Port P1 Port P2 Port P3 Port P4 Port P5 Port P6
Port P7 Port P8 Port P8_5 Port P9 Port P10
88888 8
87 88
<VCC2 ports> (4) <VCC1 ports> (4)
<VCC1 ports> (4)
M16C/62P Group (M16C/62P)
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1=VCC2.
103P1_0/D8
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P11_7
P11_6
P11_5
P11_4
P11_3
P11_2
P11_1
P11_0
P10_7/AN7_KI3
P10_6/AN6_KI2
P10_5/AN5_KI1
P10_4/AN4_KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
104
64 P12_5
P12_6
P12_7
P13_0
P13_1
P13_2
P13_3
P13_4
P13_5
P13_6
P13_7
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
VSS
P5_0/WRL/WR
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
63
105 62
106 61
107 60
108 59
109 58
110 57
111 56
112 55
113 54
114 53
115 52
116 51
117 50
118 49
119 48
120 47
121 46
122 45
123 44
124 43
125 42
126 41
127 40
128
1 102
2 101
3 100
4 99
5 98
6 97
7 96
8 95
9 94
10 93
11 92
12 91
13 90
14 89
15 88
16 87
17 86
18 85
19 84
20 83
21 82
22 81
23 80
24 79
25 78
26 77
27 76
28 75
29 74
30 73
31 72
32 71
33 70
34 69
35 68
36 67
37 66
38 65
39
VREF
AVCC
P9_7/ADTRG/SIN4
P9_6/ANEX1/OUT4
P9_5/ANEX0/CLK4
P9_4/DA1/TB4IN
P9_3/DA0/TB3IN
P9_2/TB2IN/SOUT3
P9_1/TB1IN/SIN3
P9_0/TB0IN/CLK3
P14_1
P14_0
BYTE
CNVSS
P8_7_XCIN
P8_6_XCOUT
RESET
XOUT
VSS
XIN
VCC1
P8_5/NMI
P8_4/INT2/ZP
P8_3/INT1
P8_2/INT0
P8_1/TA4IN/U
P8_0/TA4OUT/U
P7_7/TA3IN
P7_6/TA3OUT
P7_5/TA2IN/W
P7_4/TA2OUT/W
P7_3/CTS2/RTS2/TA1IN/V
P7_2/CLK2/TA1OUT/V
P7_1/RXD2/SCL2/TA0IN/TB5IN
(1)
P7_0/TXD2/SDA2/TA0OUT
(1)
P6_7/TXD1/SDA1
VCC1
P6_6/RXD1/SCL1
P1_1/D9
P1_2/D10
P1_3/D11
P1_4/D12
P1_5/D13/INT3
P1_6/D14/INT4
P1_7/D15/INT5
P2_0/AN2_0/A0(/D0/-)
P2_1/AN2_1/A1(/D1/D0)
P2_2/AN2_2/A2(/D2/D1)
P2_3/AN2_3/A3(/D3/D2)
P2_4/AN2_4/A4(/D4/D3)
P2_5/AN2_5/A5(/D5/D4)
P2_6/AN2_6/A6(/D6/D5)
P2_7/AN2_7/A7(/D7/D6)
VSS
P3_0/A8(/-/D7)
VCC2
P12_0
P12_1
P12_2
P12_3
P12_4
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
P4_2/A18
P4_3/A19
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
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