Yamaha LSI YMF715 Technical Information download pdf (Page 60)

2-14 Service Guide

Table 2-2 PCI1250 Terminal Functions

Name No. I/O Type Function

CC/BE3

CC/BE2

CC/BE1

CC/BE0

Y02

T03

N01

K01

B12

D14

B19

D20

I/O CardBus Bus Commands and Byte Enables. The

command and byte enable signals are multiplexed

on the same CardBus terminals. During the

address phase of a CardBus cycle, CC/BE3:0

defines the bus command. During the data phase,

this four-bit bus is used as byte enables. The byte

enables determine which byte paths of the full 32-

bit data bus carry meaningful data. CC/BE0 applies

to byte 0 (CAD7:0), CC/BE1 applies to byte 1

(CAD15:8), CC/BE2 applies to byte 2 (CAD23:8),

and CC/BE3 applies to byte 4(CAD31:24)

CPAR N03 A19 I/O CardBus Parity. In all CardBus read and write

cycles, the PCl1250A calculates even parity cross

the CAD and CC/BE buses. As an initiator during

CardBus cycles, the PC11250A outputs this parity

indicator with a one CCLK delay. As a target

during CardBus cycles, the calculated parity is

compared to the initiator's parity indicator; a

miscompare can result in a parity error assertion.

Cardbus Interface Control Terminals

Slot A Slot B

CAUDIO Y05 D10 I CardBus Audio. This signal is a digital input signal

from a PC Card to the system speaker. The

PCI1250A supports the binary audio mode, and

outputs a binary signal from the card to the

SPKROUT signal

CBLOCK P01 B18 I/O CardBus Lock. This signal is used to gain exclusive

access to a target

CCD1

CCD2

G03

W06

H20

C09

I CardBus Detect 1 and CardBus Detect 2. These

signals are used in conjunction with voltage sense

signals to identify ca d insertion and interrogate

cards to determine the operating voltage and card

type.

CDEVSEL R02 A18 I/O CardBus device select. The PCI1250A asserts this

signal to claim a CardBus cycle as the target

device. As a CardBus initiator on the bus, the

PCI1250A monitors this signal until a target

responds. If no target responds before time-out

occurs, then the PCI1250A will terminate the cycle

with an initiator abort.

CFRAME U01 C15 I/O CardBus cycle frame. This signal is driven by the

initiator of a CardBus bus cycle. CFRAME is

asserted to indicate that a bus transaction is

beginning. and data transfers continue while this

signal is asserted. When CFRAME is deasserted

the CardBus bus transaction is in the final data

phase.

CGNT P03 D16 I CardBus bus grant. This signal is driven by the

PCI1250A to grant a CardBus PC Card access to

the CardBus bus after ihe current data transaction

has completed.

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Yamaha LSI YMF715 Technical Information Page 60

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