1. The "LOAD SETUP DEFAULTS" function loads the system default data directly from ROM and initializes the associated hardware properly.
Hardware Design 2-52-3 System Memory ConfigurationThis mainboard supports different type of settings for the system memory. Thefollowing figur
2-6 EP-51MVP3F-AEP-51MVP3F-ABOARDATXPOWERSUPPLYFigure 2-2: Simple ATX Power ON/OFF ControllerSystem Power ON/OFF Button>This mainboard equip
AWARD BIOS 3-1CHAPTER 3AWARD BIOS SETUPAward's ROM BIOS provides a built-in setup program which allows user to modify thebasic system configu
3-2 CHAPTER 33-1 STANDARD CMOS SETUPChoose "STANDARD CMOS SETUP" in the CMOS SETUP UTILITY Menu (Fig.3-1).The STANDARD CMOS SETUP allows u
AWARD BIOS 3-3Note: The Security Option contians "setup" and "system". The "setup" indicatesthat the password setti
3-4 CHAPTER 3Quick Power On Self Test:This category speeds up Power On Self Test (POST)after you power on the computer. If it is set to Enable, BIOS
AWARD BIOS 3-5Typematic Rate Setting: This determines the typematic rate.Enabled : Enable typematic rate and typematic delay programming.Disabled:
3-6 CHAPTER 33-3 CHIPSET FEATURES SETUPChoose the "CHIPSET FEATURES SETUP" in the CMOS SETUP UTILITY menu todisplay the following menu.ROM
AWARD BIOS 3-7DRAM Timing: The default value is 60ns.60ns : 2 (faster) Burst Wait State, for 60~70ns Fast Page Mode/EDO DRAM.70ns : 3 (slower) Bur
3-8 CHAPTER 3AGP Aperture Size: The amount of the system memory that the AGP card isallowed to share. The options available are 4M, 8M, 16M, 32M, 6
EP-51MVP3F-AISA/PCI/AGP MainBoardwith Onboard PCI IDE and Super Multi-I/O.Apollo MVP3 AGPsetThe specification is subject to change without notice.TRAD
AWARD BIOS 3-93-4 POWER MANAGEMENT SETUPChoose the "POWER MANAGEMENT SETUP" in the CMOS SETUP UTILITYto display the following screen. T
3-10 CHAPTER 3B. Time-out parameters : HDD StandbyHDD Standby timer can be set from 1 to 15 minute(s).System DozeThe "System Doze" mod
AWARD BIOS 3-11RTC Alarm ResumeThis option allows you to have the system turn on at a preset time each day or on acertain day. This option is onl
3-12 CHAPTER 3PM Events:AWARD BIOS defines 7 PM Events in the power management mode (Doze &suspend). The user can initialize any PM Events to be
AWARD BIOS 3-13Resource Controlled By:The default value is Manual.Manual: The field defines that the PNP Card's resource is controlled by ma
3-14 CHAPTER 3ROM PCI/ISA BIOS(2A5LEPA9)INTEGRATED PERIPHERALSWARD SOFTWARE, INC.IDE HDD Block Mode: The default value is Enabled.Enabled : Enabl
AWARD BIOS 3-15IDE Primary Master PIO: The default value is Auto.Auto : BIOS will automatically detect the Onboard Primary Master PCI IDE HDD Acc
3-16 CHAPTER 3Onboard UART 2 Mode:The default value is standard. This field allows the User toselect the COM2 port that can support a serial Infrare
AWARD BIOS 3-17To change the password, choose the "SUPERVISOR PASSWORD or USER PASS-WORD " option from the CMOS SETUP UTILITY menu and p
3-18 CHAPTER 33-9 IDE HDD AUTO DETECTIONThe "IDE HDD AUTO DETECTION" utility is a very useful tool especially when you donot know which ki
Package ChecklistPlease check your package which should include all items listed below.If you find any item damaged or missed, please contact your su
AWARD BIOS 3-19LBA (Logical Block Addressing) mode: This is a new HDD accessing method toovercome the 528 Megabyte bottleneck.The number of cylin
3-20 CHAPTER 3Note:To support LBA or LARGE mode of HDDs, there must be some softwares involved. Allsoftwares are located in the Award HDD Service R
TECHNICAL INFORMATION 4-14-1 I/O & MEMORY MAPMEMORY MAPAddress Range Size Description[00000-7FFFF] 512K Conventional memory[8000
4-2 CHAPTER 44-2 TIME & DMA CHANNELS MAPTIME MAP: TIMER Channel 0System timer interrupt. TIMER Channel 1DRAM REFRESH request. TI
TECHNICAL INFORMATION 4-34-4 RTC & CMOS RAM MAPRTC & CMOS : 00 Seconds. 01 Second alarm.
4-4 CHAPTER 4APPENDIX A: POST CODESISA POST codes are typically output to port address 80h.01-02C00304050607C1C508090A0BPOST(hex) DESCRIPTIONReserv
TECHNICAL INFORMATION 4-50C0D0E0F101112-1314151617191A-1D1E1F-293031POST(hex) DESCRIPTIONInitialization of the BIOS Data Area. (40:ON - 40:FF)1.P
4-6 CHAPTER 4POST(hex) DESCRIPTION3233-3B3C3D3E3F-40BF414243444546-4D4E4F50511.Display the Award Plug & Play BIOS Extension message. (PnP BIOS
TECHNICAL INFORMATION 4-7POST(hex) DESCRIPTION525360616263FFUnexpected Errors:POST(hex) DESCRIPTIONB0B11.Initialize all ISA ROMs.2.Later PCI ini
4-8 CHAPTER 4APPENDIX B: CONNECTORSPS/2 KEYBOARD & MOUSE CONNECTOR: 1 Data 2 Clock 3 GND 4 NC 5 VCC Signal Name P
Contents pageChapter 1 - Introduction...
TECHNICAL INFORMATION 4-9COM1,COM2 : Serial Ports Connector Signal Name Pin Pin Signal NameDCDSINSOUTDTRGND1
4-10 CHAPTER 4FDD1 : Floppy Disk ConnectorIDE1,IDE2 : Primary, Secondray IDE Connector1 233 341 239
TECHNICAL INFORMATION 4-11Appendix C : AGP Driver for Windows 95 Installation GuideThis section provides the information for installation of Apol
4-12 CHAPTER 4b. Click on "Direct X" thenc. Click on "Direct Draw" andd. Check if there are some values existing in the "Bi
Introduction 1-1Chapter 1IntroductionThis mainboard is a high performance system hardware based on IntelPentium processor and is equipped with an
Hardware Design 2-12-1 Mainboard LayoutThis mainboard is designed with VIA Apollo MVP3 AGP/PCIset chipset which isdeveloped by VIA Corporation
2-2 EP-51MVP3F-AFigure 2-1EP-51MVP3F-A LayoutMultiplier Power Conn.83877TFDIMM2PCI#2PCI#1<BIOSSPEAKERTB-LEDRESET KEYLOCKFDD CONN.Secondary IDE
Hardware Design 2-32-2 Connectors and JumpersThis section describes the connectors and jumpers equipped in the mainboard.Please refer to Figure
2-4 EP-51MVP3F-A 1 IrDA/ASK IR CONNECTOR 51. Power LED(+)2. N/C3. GND4. Key-Lock 1 5 44. VCC3. GND2.N/C1. Speak
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